1. Technical Field
The present disclosure relates to wireless communications, and more particularly to wireless communications for direct conversion.
2. Discussion of the Related Art
Wireless communication apparatus enables long distance communications by transmitting baseband signals with high-frequency carriers.
A superheterodyne receiver down-converts radio frequency (RF) signals to intermediate frequency (IF) signals, and then down-converts the IF signals to baseband signals. The superheterodyne receiver can utilize a bandpass filter with low selectivity because the superheterodyne receiver uses the IF signals. In addition, the superheterodyne receiver has a lower risk of oscillation than a direct conversion receiver because the superheterodyne receiver amplifies signals not only in the RF stage but also in the IF stage. In addition, the superheterodyne receiver becomes less sensitive to variation of the RF signals because of the use of the IF stage. Therefore, because of these advantages, the superheterodyne receiver is widely used in wireless communications.
A direct conversion receiver directly converts RF signals to baseband signals. The direct conversion receiver has a simple configuration because the direct conversion receiver does not include an IF stage. Thus, the direct conversion receiver may be easily integrated in one chip at a lower price. The direct conversion receiver, however, has disadvantages such as oscillation, selectivity, etc. unlike the superheterodyne receiver. In particular, the direct conversion receiver has the disadvantage of a DC offset.
The direct conversion receiver typically includes a DC offset elimination circuit for eliminating the DC offset.
FIG. 1 is a circuit diagram illustrating a conventional DC offset elimination circuit.
The direct conversion receiver directly converts received RF signals to baseband signals instead of first converting the received RF signals to IF signals. A mixer 10 in the direct conversion receiver converts the received RF signals to the baseband signals. A DC offset elimination device 100 eliminates the DC offset in the baseband signals (input signal pair) inputted through a mixer load 12. That is, the DC offset elimination device 100 receives the input signal pair through an input node 101 and outputs an output signal pair through an output node 102. A variable gain amplifier 110 is disposed on a path from the input node 101 to the output node 102. The variable gain amplifier 110 amplifies the input signal pair and outputs the output signal pair. The DC offset elimination device 100 performs low-pass filtering on the output signal pair and feeds back the filtered signal pair to the input node 101, thereby eliminating the DC offset in the output signal pair. The DC offset is eliminated from the input signal pair at the input node 101 in response to the filtered signal pair.
The DC offset elimination device 100 includes a resistor network 120, an amplifier 130, a capacitor pair 140 and a transconductor 150. The resistor network 120, the amplifier 130 and the capacitor pair 140 correspond to an analog integrator circuit that performs low-pass filtering on the output signal pair. The transconductor 150 extracts the DC offset from the input signal pair at the input node 101 in response to the filtered output signal pair. At the input node 101, the input signal pair and the low-pass filtered output signal pair are separated, and the DC offset in the input signal pair is eliminated. That is, the DC offset elimination device 100 performs high-pass filtering on the input signal pair by using a DC offset elimination loop.
In the direct conversion receiver, the quality of the output signal pair relates to a cutoff frequency of the high-pass filtering, and the quality of the output signal pair is improved as the cutoff frequency decreases. In the configuration illustrated in FIG. 1, the cutoff frequency may be lowered by increasing the resistance of the resistor network 120 and the capacitance of the capacitor pair 140. A larger capacitance can be obtained when the area of a capacitor is increased. A capacitor with a large area, however, has a disadvantage when a DC offset elimination device is implemented into an integrated circuit. Also, a resistor with a large resistance may cause a parasitic capacitance. Thus, there has been a requirement for a DC offset elimination device that may be implemented into a small-sized integrated circuit.
The direct conversion receiver including the DC offset elimination device with a low cutoff frequency requires a long settling time when the direct conversion receiver is turned on. In the conventional direct conversion receiver, the cutoff frequency is increased in order to reduce the settling time, thereby degrading the quality of the signals. Accordingly, there has been a need for a DC offset elimination device having a shortened settling time but that is still capable of maintaining a high signal quality.